Reduced Instruction Set Computer (RISC) processors are well known. RISC processors have instructions that facilitate the use of a technique known as pipelining. Pipelining enables a processor to work on different steps of an instruction at the same time and thereby take advantage of parallelism that exists among the steps needed to execute an instruction. As a result, a processor can execute more instructions in a shorter period of time. Additionally, modern Complex Instruction Set Computer (CISC) processors often translate their instructions into micro-operations (i.e., instructions similar to those of a RISC processor) prior to execution to facilitate pipelining.
Many pipelined processors, especially those used in the embedded market, are relatively simple in-order machines. As a result, they are subject to control, structural, and data hazard stalls. More complex processors have out-of-order execution pipelines. These more complex processors, often referred to as out-of-order processors, schedule execution of instructions around hazards that would stall an in-order machine.
Register renaming is a technique used by out-of-order processors to avoid unnecessary serialization of program operations imposed by the reuse of logical registers. In a conventional out-of-order processor, register renaming is implemented using a custom content-addressable memory (CAM) that holds a register map. The register map identifies associations formed between physical registers and logical registers. The CAM register map is searched, for example, during instruction decode and dispatch operations to identify physical registers that hold the latest results for source logical registers specified by an instruction.
In a conventional out-of-order processor, other register status information such as, for example, information that indicates whether register data is available in a register file or off a bypass is also maintained in a custom CAM. While custom CAMs and conventional out-of-order processing techniques work for their intended purposes, they are costly to implement in terms of chip area, power consumption, and processing speed. As a result, especially in the embedded market, the number of applications in which a conventional out-of-order processor may be used is restricted.
What are needed are new techniques for implementing out-of-order processing that overcome the limitations associated with conventional techniques.